The invention pertains to the scanning of data from a number of complimentary metal-oxide semiconductor (CMOS) storage elements.
As the functionality of integrated circuits increases, and the size of integrated circuits decreases, it becomes evermore important to increase the controllability and observability of integrated circuits while decreasing the overhead required for same. A simple way to control and observe the state of storage elements in an integrated circuit is to implement a serial scan chain structure, wherein the data stored in each of a number of storage elements is downloaded into the scan chain, and then stepped from link to link of the scan chain in a serial fashion. A serial scan chain typically requires fewer transistors, less chip area, fewer external pins, etc. than parallel ports and other means for accessing a chip""s state. However, even though serial scan chains require less overhead than parallel and other forms of scanning, even serial scan chains have required the addition of two to five control signals per integrated circuit, and from 16 to 32 transistors per storage element accessed on an integrated circuit.
The scan chain link illustrated in FIG. 1 requires the use of sixteen transistors for each latch serviced by a scan chain. A first transfer gate of the link is opened and closed by a shift signal SHIFT_A, and a second transfer gate of the link is opened and closed by a shift signal SHIFT_B. When closed, the first transfer gate allows data carried on the scan chain to be input to a latch via the latch""s feedback node. The second transfer gate, when closed, allows data stored in the latch to be output to a slave latch. When the first transfer gate of a downstream link is closed, data stored in the slave latch is transferred to a latch serviced by the downstream link. Given that the latch serviced by the FIG. 1 scan chain link serves as a master latch in the link, and data is input and output to this master via the latch""s feedback node, it is necessary that shift signals SHIFT_A and SHIFT_B be asserted in an alternate and non-overlapping fashion. In this manner, shift signal SHIFT_A is asserted while shift signal SHIFT_B is at rest, thus stepping scan data into the master latch. Shift signal SHIFT_A is then de-asserted, and after a brief delay, shift signal SHIFT_B is asserted, thus stepping scan data from the master latch to the slave latch. Thereafter, shift signal SHIFT_B is de-asserted, and shift signal SHIFT_A is asserted to step scan data from the slave latch into the master latch of a downstream link. Each of the inverters following a latch node which can receive data (whether it be the storage node of the master latch, the feedback node of the master latch, or the storage node of the slave latch) is implemented as an enabled inverter so that a newly latched data value may overdrive the inverter more easily. The data stored by the FIG. 1 master latch is NORed with a signal SS to produce an output. In this manner, assertion of the SS signal allows the output of the latch to be driven to a constant value despite the stepping of various scan data values through the latch (i.e., the output of the latch can be driven to a xe2x80x9cnon-wigglexe2x80x9d state).
The scan chain link illustrated in FIG. 2 requires the use of twenty-one transistors for each latch serviced by a scan chain. The link comprises seven transfer gates. A first pair of transfer gates, or those driven by the signals SHIFT and UPDATEA, determine whether data stepped into a master latch of the scan chain link is derived from an upstream scan chain link or the latch being serviced by the FIG. 2 scan chain link. A second pair of transfer gates, or those driven by the signals NORMA and the inverse of NORMA, determine whether data loaded into the link from the latch which it services is derived from the latch""s input or output. A fifth transfer gate, or the one driven by the signal NSHIFT, is opened and closed in an out of phase relationship with respect to the transfer gate driven by the signal SHIFT. In this manner, the transfer gate driven by the signal SHIFT steps data from link to link of a scan chain, and the transfer gate driven by the signal NSHIFT steps data from master latch to slave latch within a scan chain link. A last pair of transfer gates, or those driven by the signals CKB and PRELOADA, are used to step data from a scan chain into an intermediate latch, and then finally into the latch which is being serviced by a scan chain link.
An advantage of the FIG. 1 scan chain link is that the latch being serviced serves as the master latch for the link, thus enabling a reduced transistor count for each scan chain link (i.e., sixteen transistors).
Although the above scan chain links offer various advantages, the ever increasing number of storage elements appearing in a single VLSI circuit, as well as the desire to provide better observability and testability of these storage elements, leads to a push for a reduction in the amount of overhead required to implement a scan chain structure.
In the achievement of the foregoing objects, the inventor has devised methods and apparatus for scanning data into and out of a latch. The methods and apparatus reduce the transistor count for a xe2x80x9cwigglexe2x80x9d scan chain link (i.e., one in which the output of a scanned latch is allowed to change while a scan is being performed) to eight transistors, and allow a single periodic shift signal to fully control operation of the scan chain link. The methods and apparatus also reduce the transistor count of a xe2x80x9cnon-wigglexe2x80x9d scan chain link to twenty-five, with a need for only two control signals.
A first embodiment of the invention is adapted to be implemented as part of a serial scan chain which services a plurality of latches. The first embodiment of the invention comprises a scan chain link having first and second transfer gates. The first transfer gate comprises 1) an input for receiving a scan output of a latch Nxe2x88x921 which is being serviced by the scan chain, 2) an output coupled to a latch N which is being serviced by the scan chain, and 3) a number of control inputs. The second transfer gate comprises 1) an input coupled to the latch N2) an output which provides a scan output for the latch N, and 3) a number of control inputs. The control inputs of the two transfer gates are preferably fed by a single periodic shift signal, and are designed such that the periodic shift signal alternately causes one or the other of the transfer gates to conduct.
A second embodiment of the invention is also adapted to be implemented as part of a serial scan chain which services a plurality of latches. The second embodiment of the invention comprises a scan chain link having first and second transfer gates, a latch means, and a means for loading data stored in the latch means into a latch N which is being serviced by the scan chain link. The latch means is designed to periodically receive and store a copy of data which is held in the latch N. The latch means receives a copy of data held in the latch N in response to the assertion of a signal which loads data into the latch N (i.e., preferably a clock signal). The first transfer gate comprises an input for receiving a scan output of a latch Nxe2x88x921 which is being serviced by the scan chain, an output which is coupled to a first node of the latch means, and a number of control inputs. The second transfer gate comprises an input which is coupled to a second node of the latch means, an output which provides a scan output for the latch, and a number of control inputs. Once again, the control inputs of the two transfer gates are preferably fed by a single periodic shift signal, and are designed such that the periodic shift signal alternately causes one or the other of the transfer gates to conduct.